PDF) High-Level Test Synthesis for Delay Fault Testability
PDF) Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
PDF) On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) A domain-specific approach for software development on Manycore platforms
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PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic
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PDF) Memory testing with a RISC microcontroller
Education and Information Technologies | Home
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation
PDF) Accumulator-Based Weighted Pattern Generation.
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) Efficient Test Compaction for Pseudo-Random Testing
PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places
